This invention relates to a method of controlling a polyphase inverter and a control circuit therefor wherein the inverter is controlled by using a conduction pattern prestored in a memory device such as a programmable read only memory device (P-ROM) or a mask ROM, and more particularly to a method of controlling a polyphase inverter and a control circuit therefor in which the conduction pattern stored in the ROM is determined by utilizing the characteristic of a control signal for improving the utilization efficiency of the conduction pattern.
Usually, an inverter is constituted by a number of transistors or silicon controlled rectifier elements which are connected in a bridge circuit and control signals are applied to the base electrodes of the transistors or gate electrodes of the silicon controlled rectifier elements for converting a DC power into a single phase or three phase alternating power. Although various methods of forming the control signals for the inverter have been used, since, in an inverter designed to produce alternating current of variable frequency, the number of the conduction patterns is large, a ROM or other types of arithmetic operating units are frequently used.
However, since a conduction pattern of the inverter has been stored in the ROM over one period of the pattern, the utilization efficiency of the ROM is low so that it is necessary to use a large capacity ROM in order to ensure an accurate control. Furthermore, with a ROM of a prior art capacity it has been necessary to decrease its control resolution.
These defects will be outlined in the following: Thus, FIG. 1 shows a typical prior art three phase inverter 10 comprising a bridge circuit 12 connected across a DC source E for producing three phase AC outputs. The bridge circuit 12 is made up of 6 switching transistors T.sub.r1 through T.sub.r6, two of them being connected in series to form three parallel branch circuits, and output terminals U, V and W are connected between junctions of the pairs of transistors T.sub.r1, T.sub.r4 ; T.sub.r2, T.sub.r5 and T.sub.r3 and T.sub.r6.
Base electrodes B.sub.1 through B.sub.6 of respective transistors are supplied with control signals from a control circuit to be described later to produce a three phase AC output power at the output terminals U, V and W.
Usually, a control circuit as shown in FIG. 2 has been used for the inverter shown in FIG. 1. All bits of a 5 bit frequency data signal 20 generated by a frequency data oscillator, not shown, are applied to a rate multiplier 21a to be described later in detail, while 4 bits of the signal 20 are supplied to a ROM 22, and one bit to a data selector 23.
The purpose of the rate multiplier 21a is to convert a signal f.sub.in received from an oscillator 24 into the following output signal f.sub.out : ##EQU1## where M represents a constant, and 64 a constant determined by the number of bits 5.
Thus, the rate multiplier 21a converts the oscillation frequency f.sub.in into a signal having a frequency proportional to the oscillation frequency f.sub.in. The outout signal f.sub.out of the rate multiplier 21a is supplied to a frequency divider 25 to produce an output f.sub.p expressed by the following equation: ##EQU2## where n represents the number of frequency division stages. The output f.sub.p of the frequency divider 25 is applied to a two stage counter 26 to obtain an output having a number of bits determined by the capacity of the ROM and the number of bits of a designated frequency data.
Typically, the ROM 22 has a memory capacity of 2048 words, each consisting of 8 bits. As above described, since the ROM 22 is supplied with a 4 bit signal from the frequency signal oscillator, it would receive a 7 bit signal from the counter 26. Thus, as the ROM 22 is supplied with the 4 bit signal from the frequency data oscillator, even when each one half of 8 bit data of 16 types is used, the ROM can be supplied with 32 types of the frequency data. Since the counter 26 is constructed to produce a 7 bit output, it can receive 128 signals.
With the circuit shown in FIG. 2, data have been stored in the ROM 22 in a manner as shown in FIG. 3 in which the abscissa represents the electric degrees of data designated by the output of the counter 26, while the ordinate the data designated by the frequency data oscillator.
In this manner, since 16 or 32 types of data are stored in 128 sections the resolution of one data over 360.degree. is approximately 3.degree..
These data are supplied from ROM 22 to the data selector 23 in response to a value designated by the frequency data and the output of the counter 26 for producing an AC output signal which is divided into two portions, one (3 bits) directly applied to a 6 bit register 27 and the other (3 bits) applied thereto through an inverter 28. The timings of these signals are matched by a 6 bit register 27 under the control of the output signal f.sub.p produced by the frequency divider 25 and then applied to the base electrodes B.sub.1 through B.sub.6 of the inverter transistors T.sub.r1 through T.sub.r6 to act as control signals.
Since the control circuit described above is constructed such that the ROM 22 is controlled by a 4 bit frequency designation signal and a 7 bit period division signal for producing control signals for the inverter in a ROM of a capacity of 2048 words, each consisting of 8 bits, the resolution of the angular frequency is about 3.degree. meaning a low accuracy. The accuracy can be improved by using a large capacity ROM which is expensive.